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STI4600
6 CHANNEL DOLBY AC-3(R) MPEG1/2 AUDIO DECODER
ADVANCE DATA
s s s
s s
s s
s s s s
s
s s s s s s s
(R) Single Chip Dolby* Class A AC-3 Decoder Decodes 5.1 Dolby AC-3 Digital Surround Output to 6 Channels. Downmix Modes: 1, 2, 3 or 4 Channels Karaoke Aware Mode for DVD MPEG2 Audio Decoder: Layers I and II, Data Rates up to 448 Kbit/s PCM: transparent, downsampling 96 to 48KHz Accepts MPEG-2 PES Stream Format for: MPEG-2, MPEG-1, Dolby AC-3 and Linear PCM Bitstream Input Interface: Serial or Parallel IEC-958 Output Interface Pro Logic(R) Decoder Down Mix for Dolby Pro Logic Compatible Outputs PLL for Internal 44.1 and 48KHz PCM Clock Generation On Chip Pink Noise Generator PTS Handling Control On Chip No External DRAM I C or Parallel Control Bus 27MHz Master Clock 80 Pin PQFP Package 3.3V Power Supply, I/Os 5V Compatible, 0.5m CMOS Technology
PQFP80 (Plastic Package) ORDER CODE: STI4600ACV
APPLICATIONS s DVD Consumer Players s Multimedia PC s Set Top Box s HDTV s High End Audio Equipment
* "Dolby", AC-3" and "Pro Logic" are trademarks of Dolby Laboratories
January 1997
This is preliminary information on a newproduct in development or undergoing evaluation. Details are subject to change without notice.
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1
Table of Contents
STI4600 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.1 DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.2 PIN OUT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 3 INTERNAL CIRCUIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3.1 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3.2 PLL SETUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.2.1 System PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.2.2 DAC PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.3 DECODING PROCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3.1 Decoding States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3.4 INTERFACE DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.4.1 Data Serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.4.1.1 Modes without LRCLKIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.4.1.2 LRCLKIN modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.4.2 Data Parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.4.3 Parallel control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.4.4 I C control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.4.4.1 Introduction : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.4.4.2 Protocol Description : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.4.5 PCM OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.4.5.1 Interface and Output Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.4.5.2 PCM Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.4.6 IEC output interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4 ELECTRICAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.3 AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.4 TIMING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 4.4.1 4.4.2 4.4.3 4.4.4 4.4.5 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Data Serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Data Parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Parallel Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 PCM DATA Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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Table of Contents
5 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 5.2 REGISTER MAP BY ADDRESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.3 REGISTER MAP BY FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.4 REGISTER MANUAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.4.1 Version registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.4.2 Setup and Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.4.3 PCM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.4.4 DAC and PLL Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.4.5 Channel Delay Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.4.6 IEC958 Output Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.4.7 Command Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.4.8 Interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.4.9 Interrupt Status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.4.10Decoding Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.4.11Post Decoding and Prologic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.4.12Bass Redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.4.13AC3 Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 5.4.14MPEG decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 6 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
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STI4600
1 INTRODUCTION
1.1 DESCRIPTION The STI4600 is a fully integrated Class A Dolby AC-3 decoder capable of decoding both 5.1 and 2 Channels compatible with the DVD standard. The device also decodes both MPEG1 and MPEG2 layers I and II Audio. 1.2 PIN OUT DESCRIPTION
Pin Number CONTROL INTERFACES 57 45 I C Control Interface 44 46 42 Parallel Control Interface 80 - 1 - 2 - 3 4 -7 - 8 -9 15 - 16 - 17 - 18 19 - 20 - 21 - 22 38 23 37 DATA INPUT INTERFACES Serial Data Interface 40 41 39 59 DATA OUTPUT INTERFACES 67 DAC Interface 63 64 73 74 75 IEC958 Interface (S/PDIF) 61 Name IRQ SELI2C O I Type Function Interrupt Signal (level) Select the Control Interface (parallel or serial_ I C I C Serial Data I C Clock Determine the slave address Host Data Host Address Chip Select Read/ Write Selection Data Acknowledge
The device accepts a MPEG-2 PES stream, input data can be entered either by a serial or parallel interface. The control interface can be either I C or a parallel 8-bit interface. No external DRAM is necessary for a total of 35ms surround delays.
SDAI2C SCLKI2C MAINI2CADR D0 - D1 - D2 - D3 D4 - D5 - D6 - D7 A0 - A1 - A2 - A3 A4 - A5 - A6 - A7 CS R/W WAIT
I /O I I I/ O I I I O
DSTR SIN LRCLKIN REQ PCMCLK SCLK LRCLK PCM_ OUT0 PCM_ OUT1 PCM_ OUT2 I958OUT
I I I O I/ O O O O O O O
Clock Input Data Serial Input Data Word Clock for the Input Handshake for the Data Transfer Clock Input or PLL Output Bit Clock for the DAC Word Clock for the DAC Data for the first DAC (Left/Right) Data for the second DAC (Centre/Sub) Data for the third DAC (LS/RS1) S/PDIF Signal
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STI4600
INTRODUCTION (Cont'd) PIN OUT DESCRIPTION (continued)
Pin Number STATUS INFORMATION PCM Related Information 58 60 Audio Video Synchronization 62 Other Signals 36 43 49 52 PLL INTERFACES 26 68 69 70 31 32 33 5 - 11 - 12 - 24 - 27 - 30 - 35 - 47 50 - 53 - 55 - 65 - 71 - 76 - 79 6 - 10 - 13 - 25- 28 - 29 - 34 - 48 51 - 54 - 56 - 66 - 72 - 77 - 78 14 Name Type Function
SFREQ DEEMPH PTS CLK RESET TEST SMODE CLKOUT VDADAC VCDAC VSADAC VDASYS VCSYS VSASYS GND VDD NC
O O O I I I I O VDD GND VDD GND GND VDD NC
sf= 48KHz when 0/ sf= 44. 1 when 1 Deemphasis To signal a PTS Master Clock Input Signal (27MHz) Reset Signal Input Test: Connect to VDD Test: Connect to GND
Analog DAC PLL Supply Voltage DAC PLL Filter Analog DAC PLL Ground Analog System Supply Filter System Analog System Ground Ground Power Supply Reserved Pin, tie to ground
Figure 1. Pin connections
GND GND GND GND R/W VDD VDD VDD NC D7 D6 D5 D4 D3 D2 2 D1 1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 D0 GND V DD V DD GND PCM_OUT2 PCM_OUT1 PCM_OUT0 V DD GND VSADAC VCDAC VDADAC PCMCLK V DD GND LRCLK A7 A6 A5 A4 A3 A2 A1 A0
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 VDD CLKOUT GND VDD VDD GND VDASYS VCSYS VSASYS VDD GND CLK WAIT CS LRCLKIN DSTR 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
8
7
6
5
4
3
SELI2C
SFREQ
REQ
SIN
DEEMPH
GND
GND
GND
GND
MAINI2CADR
SCLKI2C
I958OUT
RESET
TEST
SDAI2C
PTS
IRQ
VDD
VDD
VDD
VDD
SMODE
SCLK
4600-01.EPS
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STI4600
2 GENERAL DESCRIPTION
The device has 3 operating modes: - AC-3 bitstream decoding 1 to 6 channel PCM outputs, - MPEG1 Layers I and II decoding to 2 PCM channel outputs or MPEG2 layers I and II multichannel decoding, - PCM modes for CD backwards compatibility, SD PCM data processing, A Pro Logic decoder for 4 channel surround PCM output is available in each of the above three operating modes; it can be used for surround encoded digital bitstreams and in PCM mode. Additional Features - Controllable delays for centre and surround in programmable steps (e.g. for 48KHz, 0.3ms steps). - Five choices for low frequency redirection output configurations. - A pink noise generator for optimal surround sound set up. - A Digital IEC-958 output interface to be used for PCM or encoded bitstream data. - Selectable serial or parallel data control inputs. - Processing of many packetised or non-packetised input formats. - The device has a sample rate converter on chip which enables 96KHz to 48kHz downsampling. Control Interface The device has 2 control interfaces: - I C interface operating at 400kHz, - 8-bit interface with "Wait" signal handshake and interrupt request signal. Data Input Interface There are three possible ways of inputting compressed data, shown in the Table below.
Serial Input Strobed by DSTR DMA Mode Strobed by CS Parallel Input DMA Mode write to DATAIN
The compressed bitstream can be input in parallel or serial mode depending upon the value of the relevant register. If serial mode is selected, data is placed on Pin SIN, and strobed in on the rising edge of signal DSTR. If the signal REQ is asserted, then 16 more data bits can be input. REQ is deasserted when the input buffer is full. REQ polarity is programmable. If Parallel mode is selected, data can be input using DSTR as described above, or by writing to the DATAIN register usingCS. If the signal REQ is asserted, then two more bytes can be input. Output Interface The STI4600 has 2 output interfaces: - Digital IEC958 Fully IEC958 formatted, single ended CMOS/TTL output for: Encoded bitstreams according to Dolby(R) proposal for AC-3 and MPEG Audio with time stamps, linear PCM output (left and right channels, 16, 18, 20 & 24 bits), Zero output (Mute mode) - PCM Audio output Format of Input Data s Packetized Input Data - MPEG1 system streams carrying MPEG1 Audio - MPEG2 PES streams for DVD - MPEG2 PES streams s Non-Packetized Input Data - AC-3 elementary streams - MPEG1and MPEG2 Audio elementary streams (with or without extensions) - Stereo PCM data from an ADC
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STI4600
LTRT 4 DELAY PROLOGIC DECODER AC3
GENERAL DESCRIPTION(Cont'd)
73 PCM_OUT0 74 PCM_OUT1 DELAY 75 PCM_OUT2 63 SCLK
DOWNMIX
L R C Lfe Ls Rs HPF/LPF SUBWOOFER
L R C Lfe Ls Rs 6 SWITCH
SIN 41 PES PARSER SWITCH PROGRAMMABLE SWITCH PLL AND CLOCKS
LRCLKIN 39
BUFFER
64 LRCLK 26 CLKOUT
DOWNMIX L R Mute L PCM
DSTR 40
MPEG 1 MPEG 2
REQ 59 PINK NOISE GENERATOR
L R C Lfe Ls Rs
D[0..7]
36 CLK 67 PCMCLK
Figure 2. Audio Decoder Top Level Functional Diagram
A[0..7] PCM DOWNSAMPLING R 96/48 kHz PACKET FORMATTER PTS
MAINI2CADR 42
SCLKI2C 46
CONTROL
IEC958 FORMATTER Encoded
61 I958OUT
SDAI2C 44
57
38
IRQ
CS
4600-02.EPS
STI4600
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STI4600
3 INTERNAL CIRCUIT DESCRIPTION
3.1 ARCHITECTURE The STI4600 is based on a programmable core optimized for audio decoding algorithms. Dedicated hardware has been added to perform specific operations such as bitstream depacking or IEC data formatting. The arrows in Figure 3 indicate the data flow within the chip. The compressed bitstream is input via the input interface. Data is transferred on a byte basis to the FIFO. This FIFO allows burst input data up to 33Mbit/s. The input processor depacks the bitstream (Packet level).The compressed audio frames with their associated information (PTS) are stored into the circular frame buffer before the audio core decoder extracts and decodes them. Figure 3. STI4600 Architecture and Dataflow The samples are the output of the core audio decoder. The PCM unit converts the samples to the PCM format.The PCM unit controls the channel delay buffer in order to delay each channel independently. The IEC unit transmits non compressed data or compressed data. In the compressed mode the data is extracted from the circular buffer and formatted according to the IEC1937 standard. In non compressed modes the left and right PCM channels are output by the IEC unit.
1 DataIn
Input Data Interface
2
FIFO 256x8 Input Processor
IEC958 Formater
I958OUT
3 PCM Host Interface Control, Status Clocks Core Audio Decoder 5 Circular Frame Buffer Unit 4 7 6 PCMOUT 8
Channel Delay Buffer (35 ms)
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STI4600
INTERNAL CIRCUIT DESCRIPTION(Cont'd) 3.2 PLL SETUP There are two embedded PLLs in the STI4600: the system PLL and the PCM PLL. Both are used to generate clocks from the 27 MHz clock input. 3.2.1 System PLL The system PLL is used to create the system clock from the 27 MHz input clock.This PLL is software programmable. A register is used to set the frequency between 1.5 MHz up to 33 MHz in steps of 1.5 MHz. After hard reset the system clock is running at 33 MHz. An RC must be connected to the filter pin VCSYS, recommended values are 1.5 Kohms / 1nf. 3.2.2 DAC PLL This PLL is used to generate the clock for the digital to analog converter. The use of this PLL is optional. After Hard reset this PLL is disabled and the pin PCMCLK is an input of the device. To activate this PLL an internal register must be set. In this case the pin PCMCLK becomes an output. The output clock frequency can be 384x44.1KHz or 384x48 KHz, the choice is done via a host register. An RC must be connected to the filter pin VCDAC, recommended values are 10 Kohms / 2.2nf.
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STI4600
INTERNAL CIRCUIT DESCRIPTION(Cont'd) 3.3 DECODING PROCESS The decoding process in the STI4600 is done in several stages : - Parsing - Main decoding - Post decoding - Bass redirection Each of the stages can be activated or bypassed according to the configuration registers. Parsing: The bitstream parsing is in charge of discarding all the non audio information in order to transmit to the next stage only the audio elementary stream (AC3, MPEG1/2, LPCM,PCM).The parsing stage checks also the syntax of the bitstream. Two kinds of checks are done : checksum calculation and detection of expected synchronization word. The checksum is done for AC3 frame and MPEG-2 extension part. When an error occurs the bitstream is discarded, and the parser tries to recover synchronization. This leads to skip the erroneous frame at the output stage. Main decoding: The input of this stage is an elementary stream, the outputs are decoded samples. The number of output channels is defined by the downmix register (1 up to 6). The decoding formats currently supported are AC3 , MPEGI , MPEGII, LPCM. Post decoding: The post decoding includes specific PCM processing : DC filter ,deemphasis filter, Downsampling filter and also a Pro Logic decoder. Bass redirection: Figure 4. Decoding States Time Idle mode Init mode Decode mode This stage redirects the low frequency signals to the subwoofer and controls the volume of each channel. The low frequencies are extracted from the other channels (L,R,C,Ls,Rs,LFE). 3.3.1 Decoding States There are three different decoder states:Idle, Init and decode (see Figure 4). Commands to change the decoding states are described in Section 5.4.7 (eg. RUN, MUTE, PLAY). Idle mode In this mode the decoder is waiting for the RUN command. This mode should be used to initialise the configuration registers of the device. The DAC connected to the device can be initialized during this mode (set mute to 1).
Play X X Mute 0 1 Clock state Not running Running PCM Output 0 0
Init mode "Play" and "Mute" changes are ignored in this mode. The internal state of play and mute will be updated only when the decoder changes from the state "init" to "decode".The "init" phase ends when the first decoded samples are at the output stage of the device. Decode mode
Play Mute Clock state Pcm Outpu t Decoding 0 0 Not running 0 No 0 1 Running 0 No 1 0 Running Decoded samples Yes 1 1 Running 0 Yes
Soft reset
Run command
Decoder ready to play sample
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STI4600
INTERNAL CIRCUIT DESCRIPTION(Cont'd) 3.4 INTERFACE DESCRIPTION 3.4.1 Data Serial interface When serial mode is selected the STI4600 uses a four signal data interface (see Figures 12 and 13) that provides an input data lineSIN, an input CLK DSTR, a word clock input LRCLKIN and a handshake output signal REQ. The register CAN_SETUP is used to configure this serial interface, see Register Manual. 3.4.1.1 Modes without LRCLKIN In this mode the signal LRCLKIN is not used by the STI4600. The input dataSIN is sampled on the rising edge of DSTR. When the STI4600 input buffer is full the REQ signal is asserted. The polarity of REQ signal is programmable. The data must be sent most significant bits first. When the decoder cannot accept further data the REQ is deasserted, the DSTR clock must be stopped as soon as possible to avoid data loss. After the REQ is deasserted, the decoder is still able to accept data for a limited number of clock cycles. The maximum number of data that can be transmitted with respect to the change ofREQ is given by the following formula: Nbits = 23 - 6 * FDSTRB/33MHz, Maximum value is 23 bits, Minimum value is 17 bits. Table 1. CAN_SETUP Mapping
When Set bit[0] bit[1] bit[2] bit[3] The input data is one slot delayed with respect to LRCLKIN First channel when LRCLKIN is set Data are sampled on falling strobe Only the first 16 data bits are extracted When Clear The input data is not delayed First channel when LRCLKIN is clear Data are sampled on rising strobe All the bytes are extracted Name DelayMode 1 RightFirstChannel 2 FallingStrobe 4 AllSlot 8
Where: FDSTR: DSTR clock frequency, (max is 33 MHz) The polarity of REQ signal is programmable. In the above example it is active low.The REQ is deasserted (went high on figure) asynchronously from DSTR. See Figure 13 for timing details. 3.4.1.2 LRCLKIN modes These modes are used mainly for non compressed data (But they can be used also for compressed data). The LRCLKIN signal is used to make the distinction between the left and right channel. In these modes any edge of the LRCLKIN signal indicates a word boundary. The data transfer between the input interface and the FIFO is done on a byte basis. After the edge (rising or falling) of the LRCLKIN, a new byte is transferred to the first stage of the STI4600 every 8 DSTR clock cycles. If the number of time slots is not a multiple of 8, the remaining data is lost. The polarity of LRCLKIN and DSTR are programmable. The LRCLKIN can be delayed by one time slot, in order to support PCM delayed mode. The register CAN_SETUP is a 4 bit register. Each bit has specific meaning, seeTable 1 and Register Manual.
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STI4600
INTERNAL CIRCUIT DESCRIPTION(Cont'd) Example 1: Only the first byte is transfered to the STI4600 because the number of time slots is 12 (8+4). SIN and LRCLKIN are sampled on the falling edge of
LRCLKIN
DSTR.In this case SIN_SETUP=3 and CAN_SETUP= LeftFirstChannel + FallingStrobe + AllSlot = 2 + 4+ 8 =14.
DSTR
Bit 7 Bit 6
Bit 5 Bit 4
Bit 3 Bit 2
Bit 1 Bit 0
Bit 7 Bit 6
Bit 5 Bit 4
Bit 7 Bit 6
Bit 5 Bit 4
Bit 3 Bit 2
Bit 1 Bit 0
Bit 7 Bit 6
SIN
Transferred data
Discarded data DSTR. The data is in delayed mode.The register configuration is SIN_SETUP=3 and CAN_SETUP= DelayMode+ RightFirstChannel + FallingStrobe + AllSlot= 1+ 2 + 4+ 8 =15.
Example 2: Only the first 2 bytes are transfered to the STI4600 because the number of slots is 20(16+4). SIN and LRCLKIN are sampled on the falling edge of
LRCLKIN
DSTR Bit 4
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 7
SIN
Transferred data
Discarded data
Example 3: This mode is a specific mode where only the first 16 data bits are transfered. The remaining bits are
discarded. The register configuration is SIN_SETUP=3 and CAN_SETUP=DelayMode+ FallingStrobe =1+4=5.
LRCLKIN
DSTR
Bit 5 Bit 4 Bit 7
Bit 4 Bit 7 Bit 6
Bit 5 Bit 4
Bit 3 Bit 2
Bit 1 Bit 0
Bit 7 Bit 6
Bit 5 Bit 4
Bit 3 Bit 2
Bit 1 Bit 0
Bit 7 Bit 6
Bit 5 Bit 4
Bit 3 Bit 2
Bit 1 Bit 0
Bit 7 Bit 6
Bit 5 Bit 4
Bit 3 Bit 2
Bit 1 Bit 0
SIN
Transferred data
Discarded data
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Bit 7 Bit 6
Bit 5 Bit 4
STI4600
INTERNAL CIRCUIT DESCRIPTION(Cont'd) 3.4.2 Data Parallel interface In this mode the data must be presented on the 8 bit parallel host data bus. On the rising clock of DSTR the data byte is sampled by the STI4600. The signal REQ is used to signal when the input FIFO is full. When REQ is deasserted the transfer must be stopped to avoid to data loss. The host data bus is shared between the Parallel Control interface and the Data Parallel interface. To avoid conflict the DSTR signal and the CS signal must respect certain timing constraints. The timing diagram for the data parallel interface is given in Figure 14. The IC can also be controlled by a host using an I C interface or a general purpose host interface. These interfaces provide the same functions and are described in the following sections. 3.4.3 Parallel control interface The address bus A[7:0] is used to select one of the 128 register locations. (A[7] is not used in the current implementation of the devices, it can be stuck to GND). Some registers are Read/Write, and some write only. The signal R/ defines whether W the register access is a read or a write (high for read, low for write). A cycle is defined by the assertion of signalCS. In response to this signal the signal WAIT is always asserted. The address, read/write must be setup before the CS line is activated. If a read cycle is requested the data lines D[7:0] will be driven by the IC.For a write cycle the STI4600 will latch the data placed on the data lines on the rising edge CS. The timing diagrams for the parallel control interface are given in Figures 15 and 16.
3.4.4 I C control interface 3.4.4.1 Introduction : The I C unit works at up to 400 KHz in slave mode with 7 bit addressing. The pin MAINI2CADR selects the device address. When MAINI2CADR is high the address is 0x5C, when low the device address is equal to the value on the Data bus. The I C-BUS standard does not specify sub-addressing. There are thus potentially multiple ways to implement it. Any implementation that respects the standard is of course legal but a particular implementation is used by many companies. The following paragraphs describe this implementation. 3.4.4.2 Protocol Description : For write accesses only, the first data which follows the slave address is always the sub-address.This is the one and only wayto declare the sub-address. It should be noticed that the sub-address is implemented as a standard data on the I C-BUS protocol point of view.It is a sub-address because the slave knows that it must load its address pointer with the first data sent by the master. Included : I C-BUS message format examples : - sub-address initialization - sub-address + single write - sub-address + multiple write - single read (from the current address) - multiple read (starts from the current address) - sub-address + single read (combined message) - sub-address + multiple read (combined message)
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STI4600
START
SLAVE ADDRESS W
SA
SUB-ADDRESS @
SA
DATA TO @
SA
STOP
Figure 5. I C Message Formats
SUB-ADDRESS + SINGLE WRITE
START DATA TO @+1 SA DATA TO @+2
SLAVE ADDRESS W
SA
SUB-ADDRESS @
SA
DATA TO @
SA SA STOP
INTERNAL CIRCUIT DESCRIPTION(Cont'd)
SUB-ADDRESS + MULTIPLE WRITE
START
SLAVE ADDRESS W
SA
SUB-ADDRESS @
SA
STOP
SUB-ADDRESS INITIALIZATION
W : R/W BIT = WRITE SA : SLAVE ACKNOWLEDGE @ : SUB-ADDRESS VALUE
START SINGLE READ
SLAVE ADDRESS R
SA
DATA
NMA STOP
START MULTIPLE READ
SLAVE ADDRESS R
SA
FIRST DATA
MA
SECOND DATA
NMA STOP
Figure 6. I C Message Formats (Cont'd)
INTERNAL CIRCUIT DESCRIPTION(Cont'd)
START START SLAVE ADDRESS R SA DATA FROM @
SLAVE ADDRESS W
SA
SUB-ADDRESS @
SA NMA STOP
COMBINED FORMAT : SUB-ADDRESS + SINGLE READ
STAR SA DATA FROM @ MA
SLAVE ADDRESS W
SA
SUB-ADDRESS @
SA DATA FROM @+1 NMA STOP
START
SLAVE ADDRESS R
COMBINED FORMAT : SUB-ADDRESS + MULTIPLE READ
R : R/W BIT = READ SA : SLAVE ACKNOWLEDGE MA : MASTER ACKNOWLEDGE NMA : NO MASTER ACKNOWLEDGE (LAST DATA)
STI4600
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STI4600
INTERNAL CIRCUIT DESCRIPTION(Cont'd) 3.4.5 PCM OUTPUT 3.4.5.1 Interface and Output Formats The decoded audio data are output in serial PCM format. The interface consists of the following signals :
PCM_OUT0, PCM_OUT1, PCM_OUT2 : SCLK LRCLK PCMCLK PCM serial data outputs PCM clock output Left/Right channel select output PCM clock input
PCMCONF (16, 18, 20 and 24 bits mode), register; see Section 5.4.3. In 16 bits mode, data may be output either with the most significant bit first or least significant bit first selected by the contents of the output order select, PCMCONF.ORD. When PCMCONF.PREC > 16 bits, 32 bits are output for each channel. The data in front register, PCMCONF.DIF, is used to position the 18, 20 or 24 bits either at the beginning or at the end of each 32-bit frame. PCMCONF.FOR is used to select standard or I2S-compatible format when PCM.CONF.PREC > 16 bits is configured. Figure 7 and Table 2 show the differents output formats which are possible.
Output precision is selectable from 16 bits/word to 24 bits/word by setting the output precision select, Figure 7. PCM Output Formats
16 SCLK cycles LRCLK M S L S 16 SCLK cycles
PCM_OUT[2:0]
LM SS ML SS 32 SCLK cycles
L S M S
PCM_ORD = 0, PCM_PREC is 16 bits mode
PCM_OUT[2:0]
PCM_ORD = 1, PCM_PREC is 16 bits mode
LRCLK
32 SCLK cycles
PCM_OUT[2:0]
M L S 18, 20 or 24 bits S
0
M L S 18, 20 or 24 bits S
0
PCM_FORMAT = 1 PCM_DIFF = 1 PCM_FORMAT = 0 PCM_DIFF = 0 PCM_FORMAT = 0 PCM_DIFF = 1 PCM_FORMAT = 1 PCM_DIFF = 0
PCM_OUT[2:0]
0
M L S 18, 20 or 24 bits S L S
0
M L S 18, 20 or 24 bits S
PCM_OUT[2:0]
M 0 S 18, 20 or 24 bits
0
L M 0 S 18, 20 or 24 bits S
0
PCM_OUT[2:0]
MSB
M L S 18, 20 or 24 bits S
MSB
M L S 18, 20 or 24 bits S
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STI4600
INTERNAL CIRCUIT DESCRIPTION(Cont'd) Table 2. Data Alignments vs. PCM_PREC,
PCM_prec 0 : 16-bit mode 0 : 16-bit mode 1 : 18-bit mode 1 : 18-bit mode 1 : 18-bit mode 1 : 18bit mode 2 : 20-bit mode 2 : 20-bit mode 2 : 20-bit mode 2 : 20-bit mode 3 : 24-bit mode 3 : 24-bit mode 3 : 24-bit mode 3 : 24-bit mode PCM_ord 1 0 Na Na Na Na Na Na Na Na Na Na Na Na format Na Na 0 0 1 1 0 0 1 1 0 0 1 1 dif Na Na 0 1 0 1 0 1 0 1 0 1 0 1
PCM_ORD, format and dif
data sent on the PCM serial output (left bit first) {d8-d23} : 16 bits {d23-d8} : 16 bits {13*0}{0}{d23-d6} : 32 bits {0}{d23-d6}{13*0} : 32 bits {14*d23}{d23-d6} : 32 bits {d23-d6}{14*0} : 32 bits {11*0}{0}{d23-d4} : 32 bits {0}{d23-d4}{11*0} : 32 bits {12*d23}{d23-d4} : 32 bits {d23-d4}{12*0} : 32 bits {6*0}{0}{d23-d0} : 32 bits {0}{d23-d0}{7*0} : 32 bits {8*d23}{d23-d0} : 32 bits {d23-d0}{8*0} : 32 bits data[23:0] {d23-d8}{8*0} {d23-d8}{8*0} {d23-d6}{6*0} {d23-d6}{6*0} {d23-d6}{6*0} {d23-d6}{6*0} {d23-d4}{4*0} {d23-d4}{4*0} {d23-d4}{4*0} {d23-d4}{4*0} {d23-d0} {d23-d0} {d23-d0} {d23-d0}
data in sample memory
Notations : {5*0} means {00000} and {4*d12} represents the following binary word {d12,d12,d12,d12} PCM_DIF = 1, PCM_FORMAT = 0 is compatible with I2S format. The polarity of the PCM serial output clock, SCLK and LRCLK are selected by the INV_SCLK and INV_LRCLK registers, respectively. Figure 8. SCLK polarity
Figure 8 shows the two polarities of SCLK. Normally, the DAC will sample LRCLK and the PCMDATA on the rising edge of SCLK in the first case, and on the falling edge of SCLK in the second. The first option (INV_SCLK=0) is the one normally used in I2S systems. Figure 9 shows how the polarity of LRCLK is selected. The second option (INV_LRCLK=1) is compatible with the I2S format. See Section 4.4.5 for data output timing.
SCLK
SCLK
LRCLK, PCM_OUT[2:0] INV_SCLK= 0
LRCLK, PCM_OUT[2:0] INV_SCLK= 1
Figure 9. LRCLK polarity
left LRCLK right left right
INV_LRCLK= 0
INV_LRCLK= 1
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STI4600
INTERNAL CIRCUIT DESCRIPTION(Cont'd) 3.4.5.2 PCM Clock Generation The PCM serial clock SCLK is derived from the clock input PCMCLK. The frequency of PCMCLK may be equal to the PCM output bit rate, or it may be an integer multiple of this, allowing the use of oversampling D-A converters. SCLK is derived from PCMCLK by dividing it by the contents of the divider register, PCM_DIV. This number defines the ratio of the frequency of the PCM bit clock, SCLK, to that of PCMCLK, according the relationship: Fsclk = F PCMCLK / (2 x (PCM_DIV+1)) The value of PCM_DIV=0 is reserved. If this number is loaded, the divider is bypassed and the frequency of SCLK is equal to the frequency of PCMCLK.
The PCM_DIV register must be set up before the output of SCLK starts. This can be done by first disabling PCM outputs, by de-asserting the MUTE and PLAY commands and then writing into the PCM_DIV register. Once the register is setup, the MUTE and/or PLAY commands can be asserted. PCM_DIV can not be changed "on the fly". The frequency of LRCLK is given by: F lrclk = Fsclk / 32 ; for 16 bit PCM output F lrclk = F sclk /64 ; for 18, 20 or 24 bits PCM output. 3.4.6 IEC output interface The IEC output pad is a TTL output pad with slew rate control. The output DC capability is 4 mA.The voltage drop is 3V. This output must be connected to a TTL driver before the transformer.
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STI4600
4 ELECTRICAL SPECIFICATIONS
4.1 ABSOLUTE MAXIMUM RATINGS Maximum limits indicate where permanent device damage occurs. Continuous operation at these limits is not intended and should be limited to
Symbol VDD VI, VO TSTG TOPER Power Supply Voltages on Input and Output Pins Storage Temperature Ambient Operating Temperature Parameter
those conditions specified in section 4.2 DC ELECTRICAL CHARACTERISTICS.
Value -0.5, 6 - 0.5, 5.25 -65, +150 0, +70 Unit V V C C
4.2 DC ELECTRICAL CHARACTERISTICS Operating conditions: VDD = 3.3V + 0.3V, Tamb = 0 to 70C unless otherwise specified
Symbol Parameter Test Conditions Value Min. Typ. Max. Unit
VDD IDD VIL VIL VIH VIH
VOL VOH C IN
Operating Voltage Average Power Supply Current Input Logic Low Voltage Input Logic Low Voltage Input Logic High Voltage Input Logic High Voltage Input Leakage Current Inputs I/Os Output Logic Low Voltage Output Logic High Voltage Input Capacitance
3.0 C LOAD = 50pF on all outputs fprimary = 27MHz, all inputs at VDD or 0V Except CLK CLK Except CLK CLK VDD = 3.6V, 0 < VIN < VDD ILOAD = 0.2 to 5mA depending on the pin ILOAD = 0.2 to 5mA depending on the pin Bidirectional Pads, Input Pads
3.3 220
3.6 250 +0.8 +0.6 5.25 5.25 -10 -10 0.4 10
V mA V V V V A A V V pF
-0.3 2.0 2.5 -10 -10 2.4
4.3 AC ELECTRICAL CHARACTERISTICS Test conditions: VDD = 3.3V + 0.3V, Tamb = 0 to 70C unless otherwise specified Test Loads Figure 10. Test Load Circuit
Output D7-D0, REQ, WAIT IRQ A7-A0 Other Outputs IOL 500A 5mA 200A 200A IOH 500A 0 200A 200A CL 50pF 50pF 50pF 50pF VREF 1.5V 3.6V 1.5V 1.5V
OUTPUT CL VDD IOL
Notes: All values need to be characterised, values given are for guidance only.
Vref
IOH
3520A-72.EPS
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STI4600
ELECTRICAL SPECIFICATIONS(Cont'd) 4.4 TIMING DIAGRAMS Timings other than rise and fall times are specified with respect to a threshold of 1.5V. 4.4.1 Clock Figure 11. Clock Signals thigh 2V CLK 0.8V
3520A-73.EPS
tlow
T
Symbol
Parameter
Value Min. Typ. Max.
Unit
T THIGH TLOW
Primary Clock Period (see note 1) Clock High Time Clock Low Time
37ns 10 10
ns ns ns
Note 1: This corresponds to a maximum primary clock frequency of 27MHz.
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STI4600
ELECTRICAL SPECIFICATIONS(Cont'd) 4.4.2 Data Serial interface Register configuration: "SIN_SETUP"=1 and "CAN_SETUP"=Don't care
DSTR
SIN
TSINSH
TSINHD
DSTR
REQ TPREQ
Symbol FDSTRBSERIAL TDSTRBLOW TDSTRBHIGH TSINSH TSINHD TPREQ
Parameter DSTR Max frequency in serial mode DSTR low pulse DSTR high pulse SIN set-up time to DSTR rising edge SIN hold time from DSTR rising edge Propagation time from DSTR rising to REQ high
Min 5 5 5 5 120
Max 33
200
Unit Mhz ns ns ns ns ns
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STI4600
ELECTRICAL SPECIFICATIONS(Cont'd) 4.4.3 Data Parallel interface
DSTR
DATA
TDATASH
TDATAHD
REQ REQ
TPREQ
Note: Register configuration is "SIN_SETUP"=0 and "CAN_SETUP"=don't care.
Symbol FDSTRBPARA TDSTRBLOW TDSTRBHIGH TDATASH TDATAHD TPREQ Parameter DSTR Max frequency in parallel mode DSTR low pulse DSTR high pulse DATA set-up time to DSTR rising edge DATA hold time from DSTR rising edge Propagation time from DSTR rising to REQ deasserted Min 5 5 5 5 120 200 Max 4 Unit Mhz ns ns ns ns ns
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STI4600
ELECTRICAL SPECIFICATIONS(Cont'd) 4.4.4 Parallel Control Interface Figure 12. Write Access
TCHCL
DCS
A TSADR
Address THADR
DATA
Data THDATA
TSDATA
R/W TSRWB TWAITW THRWB
WAIT TWON TWHCH TWOFF
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STI4600
ELECTRICAL SPECIFICATIONS(Cont'd) Figure 13. Read Access
TCHCL
DCS
A TSADR
Address THADR
DATA TACC
Data
R/W TSRWB TWAITR THRWB
WAIT TWON TWHCH TWOFF
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STI4600
ELECTRICAL SPECIFICATIONS(Cont'd)
TSADR TSDATA TSRWB THADR THDATA THRWB TWAITW TWAITR TCHCL TWOFF TWON TWHCH TACC Min 5 ns 5 ns 5 ns 0 ns 5 ns 0 ns 0.5 Tsys+10 25 ns 1.5 Tsys+10 55 ns 2 Tsys + 10: 70 ns 5 ns 5 ns 0 ns Tsys+10 40 ns 2 Tsys+10 70 ns Max Hadr to DCS set-up time Hdata to DCS set-up time Hrwb to DCS set-up time Hadr to DCS hold time Hdata to DCS hold time Hrwb to DCS hold time 1.5 Tsys+10 55 ns 2.5 Tsys+10 85 ns Maximum wait time when writing Maximum wait time when reading DCS high to DCS low DCS high to WAIT off DCS low to WAIT on WAIT high to DCS high DCS low to Host Data ready
Note: TSYS is the system clock period = 1/33 MHz = 30ns
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STI4600
ELECTRICAL SPECIFICATIONS(Cont'd) 4.4.5 PCM DATA Output Timing
SCLK
PCM_OUT[2:0], LRCLK
+/- 2ns max
INV_SCLK = 0
SCLK
PCM_OUT[2:0], LRCLK
+/- 2ns max
INV_SCLK = 1
PCMCLK
SCLK,PCM_OUT[2:0], LRCLK 20 ns max
Note: . Output pads SCLK, PCM_OUT[2:0] and LRCLK are assumed equally loaded.
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STI4600
5 REGISTER DESCRIPTION
5.1 INTRODUCTION The STI4600 device includes 128 registers. In this document only the user registers are described. The undocumented registers are reserved. These registers must never be accessed (in Read or Write). The Read only registers must never be written. Meaning of the abbreviations: 5.2 REGISTER MAP BY ADDRESS
Addr 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F Name VERSION IDENT RESERVED RESERVED RESERVED SFREQ EMPH INTEL INTEH INTL INTH RESERVED SIN_SETUP CAN_SETUP DATAIN ERROR SOFTRESET PLLSYS PLLPCM PLAY MUTE RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED Addr 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F Name SYNCSTATUS ANCCOUNT HEAD[31:24] HEAD[23:16] HEAD[15:8] HEAD[7:0] PTS[33] PTS[31:24] PTS[23:16] PTS[15:8] PTS[7:0] USER STREAMSEL DECODESEL BAL_LR PACKET_LOCK AUDIO_ID_EN AUDIO_ID AUDIO_ID_EXT SYNC_LOCK PCMDIVIDER PCMCONF PCMCROSS LDLY RDLY CDLY SUBDLY LSDLY RSDLY PCMUPDATE IEC958_CMD IEC958_CAT Addr 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F Name IEC958_CONF IEC958_STATUS PDEC BAL_SUR PL_AB PL_DWNX OCFG PCM_SCALE DECODE_LFE/SKIP_LFE COMP_MOD/PROG_NO HDR/DRC LDR RPC KARAMODE/MC_OFF DUAL_MODE/MPEG_DUAL DOWNMIX DWSMODE SOFTVER RUN SKIP_FRAME REPEAT_FRAME IEC958-NULL-BURST STATUS0 STATUS1 STATUS2 STATUS3 STATUS4 STATUS5 STATUS6 STATUS7 PCMCANCEL PCMFORCECROSS NA UND NC RO WO R/W R/WS COMMENT Not Applicable Undefined No Change Read Only Write Only Read and Write Read, Write in specific mode
Note 1: Reserved Registers should not be written to. Note 2: Addresses 20 through 3F contain reserved registers only.
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STI4600
REGISTER DESCRIPTION(Cont'd) 5.3 REGISTER MAP BY FUNCTION Version (Section 1.4.1)
HEX 0x00 0X01 0X71 DEC 0 1 113 NAME VERSION IDENT SOFTVER
COMMAND (Section 1.4.7)
0x10 0X72 0X13 0X14 0X73 0X74 16 114 19 20 115 116 SOFTRESET RUN PLAY MUTE SKIP_FRAME REPEAT_FRAME
Setup + Inputs (Section 1.4.2)
0x11 0X0C 0X0D 0X0E 17 12 13 14 PLLSYS SIN_SETUP CAN_SETUP DATAIN
Interrupt (Section 1.4.8)
0x07 0X08 0X09 0X0A 7 8 9 10 INTEL INTEH INTL INTH
PCM Configuration (Section 1.4.3)
0x54 0X55 0X56 0X7E 0X7F 84 85 86 126 127 PCMDIVIDER PCMCONF PCMCROSS PCMCANCEL PCMFORCECROSS
Interrupt Status (Section 1.4.9)
0x40 0X41 0X42 0X43 0X44 0X45 0X46 0X47 0X48 0X49 0X4A 0X4B 0X0F 64 65 66 67 68 69 70 71 72 73 74 75 15 SYNCSTATUS ANCCOUNT HEAD[31:24] HEAD[23:16] HEAD[15:8] HEAD[7:0] PTS[33:32] PTS[31:24] PTS[23:16] PTS[15:8] PTS[7:0] USER ERROR
DAC and PLL Configuration (Section1.4.4)
0x05 0X06 0X12 5 6 18 SFREQ EMPH PLLPCM
Channel Delay Setup (Section1.4.5)
0x57 0X58 0X59 0X5A 0X5B 0X5C 0X5D 87 88 89 90 91 92 93 LDLY RDLY CDLY SUBDLY LSDLY RSDLY PCMUPDATE
Decoding (Section 1.4.10)
0x4C 0X4D 0X40 0X4F 0X50 0X51 0X52 0X53 Decoding algorithm STREAMSEL DECODESEL System synchronization 64 SYNCSTATUS 76 77 79 80 81 82 83 PACKET_LOCK AUDIO_ID_EN AUDIO_ID AUDIO_ID_EXT SYNC_LOCK
IEC958 Output Setup (Section1.4.6)
0x5E 0X5F 0X60 0X61 0X75 94 95 96 97 117 IEC958_CMD IEC958_CAT IEC958_CONF IEC958_STATUS IEC958-NULL-BURST
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STI4600
REGISTER DESCRIPTION(Cont'd) Post Decoding and Pro logic (Section1.4.11)
0x70 0X62 0X64 0X65 112 98 100 101 DWSMODE PDEC PL_AB PL_DWNX
Note: The titles indicate the appropriate section of the specification.
Bass Redirection (Section 1.4.12)
0x66 0X67 0X4E 0X63 102 103 78 100 OCFG PCM_SCALE BAL_LR BAL_SUR
AC3 Configuration (Section1.4.13)
0x68 0X69 0X6A 0X6B 0X6C 0X6D 0X6E 0X6F 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7C 104 105 106 107 108 109 110 111 118 119 120 121 122 123 124 125 DECODE_LFE COMP_MOD HDR LDR RPC KARAMODE DUAL_MODE DOWNMIX AC3_STATUS0 AC3_STATUS1 AC3_STATUS2 AC3_STATUS3 AC3_STATUS4 AC3_STATUS5 AC3_STATUS6 AC3_STATUS7
MPEG Configuration (Section1.4.14)
0x68 0X69 0X6E 0X6A 0X6D 0X6F 0X76 0X77 0X78 0X79 0X7A 0X7B 0X7C 0X7D 104 105 106 110 109 111 118 119 120 121 122 123 124 125 SKIP_LFE PROG_NO MPEG_DUAL DRC MC_OFF DOWNMIX MP_STATUS0 MP_STATUS1 MP_STATUS2 MP_STATUS3 MP_STATUS4 MP_STATUS5 MP_STATUS6 MP_STATUS7
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STI4600
REGISTER DESCRIPTION(Cont'd) 5.4 REGISTER MANUAL 5.4.1 Version registers VERSION - Version
7 00 6 5 4 3 2 1 0 71
SOFTVER - Software Version
7 6 5 4 3 2 1 0
Address : Type : Software Reset : Hardware Reset:
0x00 R0 NA NA
Address : Type : Software Reset : Hardware Reset:
0x71 R/W NC UND
Description The VERSION register is read-only and is used to identify the IC on an application board. The version register holds the cut number (binary decimal encoded). The version numbers are defined as below: First PQFP120 cut, version number is: 0x10 First PQFP80 cut, version number is: 0x20 IDENT - Identify
7 01 6 5 4 3 2 1 0
Description The SOFTVER register is the version of the microcode which is running on the device. This register is updated just after a soft reset of the device. Today this register is not used. 5.4.2 Setup and Inputs PLLSYS - System PLL Setup
7 11 6 5 4 BYP DIS 3 2 1 DIV[4:0] 0
Address : Type : Software Reset : Hardware Reset: Description
0x11 R/W NC 0x16
Address : Type : Software Reset : Hardware Reset:
0x01 RO NA NA
Description IDENT is a read-only register and is used to identify the IC on an application board. IDENT always has the value "0xAC".
This PLL creates the system clock from the 27 MHz clock input. The PLL can be bypassed and disabled. The frequency of the system clock is related to the value of the divider: SYSCLK= 1.5 MHz *Div Min freq : = 3 MHz, Max freq should be less or equal to 33 MHz When a Hardreset occurs the PLL is enabled and runs at 33 MHz.When a "softreset" occurs this register is not changed and the PLL runs as before the softreset. BYP : BYPASS. When set the PLL is bypassed CLKSYS= CLKIN DIS : Disabled. When set the PLL is disabled (not running) DIV[4:0] : Clock divider of the PLL
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STI4600
REGISTER DESCRIPTION(Cont'd) SIN_SETUP - Input Data Setup
7 0C 6 5 4 3 X 2 POL 1 0 IMODE
CAN_SETUP - A/D Converter Setup
7 0D 6 5 4 3 16 2 1 SAM FIR 0 PAD
Address : Type : Software Reset : Hardware Reset: Description
0x0C R/W NC 0
Address : Type : Software Reset : Hardware Reset: Description
0x0D R/W NC 0
This register is used to configure the input data interfaces. The register must be set before sending data to the IC. The mapping of the register is described below. The two LSB of "SIN_SETUP" details which interface will be used. The bit (bit two of SIN_SETUP) is used to configure the polarity of the handshake signal "REQ". When the POL bit is high the "REQ" pin meaning is inverted, and the data must be input when "REQ" is "0". When POL is low, The data must be input when "REQ" is "1". The data must be sent to the device MSB first. X : Reserved, not used POL : Polarity of the REQ signal IMODE[1:0]:Input Mode IMODE is used to configure the data input interface. The configuration of the 3 possible interfaces is shown below:
Mode 0 1 2 3 Mode Parallel input (DSTR + Data[7:0] + REQ) Serial input (DSTR + SIN + REQ) Not used A/D input (DSTR + LRCLKIN + REQ + SIN)
CAN_SETUP is used to configure the STI4600 when receiving data from an A/D Convertor. Also see SIN_SETUP register. 16 : When clear the slot count is 32 but only the 16th are extracted. SAM : When set, data is sampled on the falling edge of the bit-clock (DSTR) FIR : When set the first channel (Left) is with Lrclkin= 1 PAD : When set the Lrclkin is delayed by one cycle (Padding mode) DATAIN - Data Input
7 0E 6 5 4 3 2 1 0
Address : Type : Software Reset : Hardware Reset: Description
0x0E WO NA NA
When the IC is configured in mode 3, the input data comes from an A/D converter. In this case the "CAN_SETUP" register is used to configure the IC with respect to the A/D data format.
Data can be fed into the STI4600 by using this register instead of the dedicated interface. There is no need to byte-align the bit-stream when using this register.
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STI4600
REGISTER DESCRIPTION(Cont'd) 5.4.3 PCM Configuration PCMDIVIDER - Divider for PCM Clock
7 6 5 4 3 2 1 0
PCMCROSS - CROSS PCM CHANNELS
7 6
56 Address : Type : Software Reset : Hardware Reset: Description
5 4 CLR[1:0]
3 2 CSW[1:0]
1 0 LRS[1:0]
54 Address : Type : Software Reset : Hardware Reset: Description The PCM divider must be set according to the formula below, where Sclk is the bit clock for the DAC. When Div is set to 0,Sclk is equal to PcmClk. Div = (PcmClk/ (2 x Sclk)) -1 When the internal PLL is used, PcmClk=384 x fs. The formula becomes Div = (192 x Fs/Sclk) -1 If Sclk is 32 x Fs (common case with the 16 bit DAC), Div must be set to 5. PCMCONF - PCM Configuration
7
0x54 R/W UND UND
0x56 R/W NC UND
CLR[1:0] : Cross left and right channels. 00: When 00, Left channel is mapped on the left output, Right channel is mapped on the Right output. 01: When 01, Left channel is duplicated on both outputs. 10: When 10, Right channel is duplicated on both outputs. 11: When 11, Right channel and Left channel are toggled. CSW[1:0] : Cross Centre and Subwoofer LRS[1:0] : Cross Left and Right surround PCMFORCECROSS - Enable PCMCROSS
7 6 5 4 3 2 1 0
55
6 5 ORD DIF
4 3 2 1 0 INV FOR SCL PREC[1:0]
7F Address : Type : Software Reset : Hardware Reset: Description Enables the PCMCROSS Function. 0x7F R/W NC UND
Address : Type : Software Reset : Hardware Reset: Description
0x55 R/W NC UND
: PCM Order : PCM_DIFF. If set to zero, right padded. INV : Invert LRCLK FOR : FORMAT. If 0 the format is I2S, if 1 the format is Sony format. SCL : INVERT SCLK PREC[1:0]: PCM Precision. 0: 16 bit mode (16 slots) 1: 18 bit mode (32 slots) 2: 20 bit mode (32 slots) 3: 24 bit mode (32 slots)
ORD DIF
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STI4600
REGISTER DESCRIPTION(Cont'd) PCMCANCEL - FORCE PCM Output
7 6
5.4.4 DAC and PLL Configuration
1 LS 0 RS
7E Address : Type : Software Reset : Hardware Reset: Description
5 L
4 R
3 C
2 SW
SFREQ - Sampling Frequency
5 4 3 2 1 0
05 0x7E R/W NC UND Address : Type : Software Reset : Hardware Reset: Description SFREQ is a status register which holds the code of the current sampling frequency. Bit 0 of SFREQ is directly connected to the pin SFREQ. The "SFREQ" pin is used to indicate if the sampling frequency is 48KHz or 44.1KHz (this information can be used by a DAC). The value in SFREQ is associated with the following frequencies
Value 0 1 2 3 4 8* 9* 10* FRE48 44.1 32 not 96 24 22.05 16 QUENCY KHz KHz KHz used KHz KHz KHz KHz
0x05 R/WS NC 0
Used to force PCM output to zero. L : Force Left surround channel to zero when set. R : Force Right surround channel to zero when set. C : Force Centre surround channel to zero when set. SW : Force Subwoofer surround channel to zero when set. LS : Force Left surround channel to zero when set. RS : Force Right surround channel to zero when set.
*Note: Values 8, 9, and 10 are intended for future versions of the STI4600. They are not supported in the current version. EMPH - Emphasis
5 4 3 2 1
06 Address : Type : Software Reset : Hardware Reset: Description E 0x06 R/Ws NC 0
0 E
: Bit 0 of the EMPH register is directly connected to the pin "DEEMPH".
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REGISTER DESCRIPTION(Cont'd) PLLPCM - PCM PLL Disable 12 Address : Type : Software Reset : Hardware Reset: Description When a Hard reset occurs the PLL is disabled. The host must write 0xD2 in this register to enable it. When a Soft reset occurs the register remains unchanged. RP : Run PLL. When high the DAC PLL is running. DP : Disable pad. When low the PCM clock divider is enabled. 5.4.5 Channel Delay Setup The unit for the delay is a group of 16 samples.The maximum delay is 35 ms. The sum of all the delays must be under 1680/16=35 ms * 48 KHz. When only one surround channel is present (Prologic or other mode), the right surround delay must be clear, the left delay channel is used for both surround channels. LDLY - Left Channel
7 6 5 4 3 2 1 0 1 RP 0 DP
RDLY - Right Channel
7 6 5 4 3 2 1 0
58 Address : Type : Software Reset : Hardware Reset: 0x58 R/W NC UND
0x12 R/W NC 1
CDLY - Centre Channel
7 6 5 4 3 2 1 0
59 Address : Type : Software Reset : Hardware Reset: 0x59 R/W NC UND
SUBDLY - Subwoofer Channel
7 6 5 4 3 2 1 0
5A Address : Type : Software Reset : Hardware Reset: 0x5A R/W NC UND
LSDLY - Left Surround Channel
7 6 5 4 3 2 1 0
5B Address : Type : Software Reset : Hardware Reset: 0x5B R/W NC UND
57 Address : Type : Software Reset : Hardware Reset: 0x57 R/W NC UND
RSDLY - Right Surround Channel
7 6 5 4 3 2 1 0
5C Address : Type : Software Reset : Hardware Reset: 0x5C R/W NC UND
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REGISTER DESCRIPTION(Cont'd) PCMUPDATE - PCM Update
7 6 5 4 3 2 1 0
IEC958_CONF - IEC958 PCMCLK Divider
7
5D Address : Type : Software Reset : Hardware Reset: Description Must be set to update the delay 5.4.6 IEC958 Output Setup IEC958_CMD - IEC958 Control
7 6 5 4 3 2 1 0
60 0x5D R/W 0 0
6 SM
5 OP
4
3
2 1 DIV[4:0]
0
Address : Type : Software Reset : Hardware Reset: Description SM
0x60 R/W NC UND
5E Address : Type : Software Reset : Hardware Reset: Description This register is the control register. Several modes are available, the mode is selected by value:
Value Description The IEC958 is not working, the output line is idle. The value of the output line is determined by the value of bit 5 of the register IEC958_CONF. The line can be stuck to VDD or to GND. "Muted" mode: The outputs are PCM null data. "PCM" mode: The outputs are PCM data. Only the first two decoded channels (Left and Right) are transmitted. "Encoded": The compressed bitstream is transmitted (See IEC1937 standard)
0x5E R/W NC UND
: SYNC MUTE Mode, must be set to zero. OP : Line idle state level. The state of the interface when the interface is off. DIV[4:0] : This field is the PCMCLK divider. It must be set according to the formula: In 16 bit mode: IECDIV=(1+PCMDIV)/2-1 In 32 bit mode: IECDIV=PCMDIV The table below shows the relationship between the value of the IEC divider and the value of the PCM divider described in Section 5.4.3.
PCM IEC Divider Mode Description Divider Value Value 5 PCMCLK=384 Fs, DAC is 16bit mode 2 PCMCLK= 256 Fs, DAC is 16 bit 3 1 mode PCMCLK= 384 Fs, DAC is 32 bit 2 2 mode PCMCLK= 256 Fs, DAC is 32 bit 1 1 mode
0
"Off" mode
1
MUT
IEC958_CAT - Category Code
7 6 5 4 3 2 1 0
2
PCM
5F Address : Type : Software Reset : Hardware Reset: 0x5F R/W NC UND
3
ENC
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STI4600
REGISTER DESCRIPTION(Cont'd) IEC_STATUS - IEC Status Bit
7 6 5 4
5.4.7 Command Registers SOFTRESET - SOFT RESET
0
61 Address : Type : Software Reset : Hardware Reset: Description 0x61 R/W NC UND
3 2 1 0 SFR PRE COP COM
10 Address : Type : Software Reset : Hardware Reset: Description When this register is written, a soft reset occurs. The command registers and the interrupt registers are cleared.The decoder goes into idle mode. RUN - RUN Decoding
0
0x10 W0 NA NA
This register is used to set the value of the status bit in the IEC958 data stream. SFR : 44.1KHz sampling frequency bit PRE : Preemphasis data bit COP : Copy bit COM : Compress data bit This bit must be set to one in compressed mode and must be clear in non compressed mode. IEC958_NULL_BURST - IEC958 Null Burst Data Length
7 6 5 4 3 2 1 0
72 Address : Type : Software Reset : Hardware Reset: Description 0x72 R/W 0 0
75 Address : Type : Software Reset : Hardware Reset: Description In "compressed" mode, a burst of null data is sent when there is no more data to transmit (due to an error or a gap in the incoming bit-stream). This register is used to set the length of the burst. The length of the burst in "IEC958 sub-frame" unit. The length of the burst is (n+1), where n is the content of this register. This register must always be loaded with an odd value. We recommend to set this register to "7". PLAY - PLAY
0
0x75 R/W NC UND
After a soft or hard reset the decoder is in idle mode. The decoder stays in this mode until the register "RUN" is set. In run mode the decoder takes into account the state of all the configuration registers and begins to decode.
13 Address : Type : Software Reset : Hardware Reset: Description The PLAY command is handled according to the state of the decoder (see section 3.3.1). PLAY only becomes active when the decoder is in DECODE mode. 0x13 R/W 0 0
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REGISTER DESCRIPTION(Cont'd) MUTE - MUTE
0
REPEAT_FRAME - Repeat a Frame
7 0
14 Address : Type : Software Reset : Hardware Reset: Description The MUTE command is handled according to the state of the decoder (see section 3.3.1). MUTE sets the clock running. SKIP_FRAME - Skip a Frame
7 0
74 0x14 R/W 0 0 Address : Type : Software Reset : Hardware Reset: Description In this case the previous frame is repeated. When the register is taken in account, the decoder clears it. 0x74 R/W 0 0
73 Address : Type : Software Reset : Hardware Reset: Description When this register is set to one, the decoder clears it and then skips a frame.The number of samples in a frame depends on the nature of the frame, see table.
Decoding type AC3 MPEG layer 2 MPEG layer L-PCM PCM Sample count 1536 1152 384 80 NA
0x73 R/W 0 0
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REGISTER DESCRIPTION(Cont'd) 5.4.8 Interrupt registers INTE - Interrupt Enable
7 08 07 INTE[15:8] INTE[7:0] 0
INT - Interrupt
7 0A 09 INT[15:8] INT[7:0] 0
Address : Type : Software Reset : Hardware Reset:
0x08-0x07 R/W 0 0
Address : Type : Software Reset : Hardware Reset:
0x0A-0x09 RO 0 0
Description The audio decoder contains a 16 bit interrupt register associated with a 16 bit "enable" register. A bit set in this register will enable the corresponding interrupt. The interrupt associated with each bit is given in the register INT description.
Description An interrupt is signalled whenever one of the bits of INT become set. This can only occur if the corresponding bit is set in the INTE register. The Table below shows the condition indicated by each bit.
# Name Condi tion Signalled 0 SYN Change in synchronization status (2) 1 HDR Valid Header registered (2) 2 ERR Error Detected(2) 3 SFR Sampling frequency changed (1) 4 DEM De-emphasis changed (1) 5 BOF First bit of new frame at output stage (1) First bit of new frame with PTS at output 6 PTS stage (2) Ancillary data registered (2), Not implement7 ANC ed 8 PCM Pcm output underflow (1) 9 FBF Not implemented 10 FBE Not implemented 11 FIO FIFO input has overflowed (1) 12 TBD Reserved (1) 13 TBD Reserved (1) 14 USR Reserved (2) 15 TBD Reserved
(1) Cleared when the interrupt register is read or when a Reset occurs (2) Cleared when the corresponding register is read, or when a reset occurs
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REGISTER DESCRIPTION(Cont'd) 5.4.9 Interrupt Status registers SYNCSTATUS - Synchronization Status
7 0
HEAD4 - HEADER 4 register
AC-3 7 0 7 0 7 0 6 0 6 0 6 0 5 0 5 0 5 0 4 0 4 0 4 0 3 0 3 0 3 0 2 1 0 BSMOD 1 DR 1 0 0 K 0 0
40 Address : Type : Software Reset : Hardware Reset: Description On read the synchronization status interrupt bit is cleared (INT.SYN is cleared). ANCCOUNT - Ancillary Data
7 0
0x40 RO UND UND
MPEG-2
2 0 2 0
OTHER
Address : Type : Software Reset : Hardware Reset: Description
0x42 RO UND UND
41 Address : Type : Software Reset : Hardware Reset: Description On read the ancillary data interrupt bit is cleared (INT.ANC is cleared). 0x41 RO UND UND
This register contains header data HEAD[31:24]. The contents depend on the type of the frame. HEAD4[7:3] = 0000 in all cases AC-3 HEAD4[2:0] = BSMOD if an AC-3 frame MPEG-2 HEAD4[2] = 0, HEAD4[1] = DR. Dynamic range exists HEAD4[0] = K. K=0 in normal mode, K=1 in Karaoke mode. OTHER In all other types of frame HEAD4[2:0] = "000"
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REGISTER DESCRIPTION(Cont'd) HEAD3 - HEADER 3 register 43
7 0 0 0 0 DTYPE 46 47 48 49 4A
PTS - PTS
7 PTS[33:32] PTS[31:24] PTS[23:16] PTS[15:8] PTS[7:0] 0
Address : Type : Software Reset : Hardware Reset: Description
0x43 RO UND UND
This register contains header data HEAD[23:16]. HEAD3[7:5] = "000" in all cases HEAD3[4:0] = DTYPE DTYPE is the data type and the meaning is as follows:
0000: 0001: 0100: 0101: 0110: 1000: 1001: Null data or Linear PCM AC-3 MPEG-1 Layer I MPEG-1 Layer 2 or MPEG-2 wo extension MPEG-2 Layer 2 with extension MPEG-2 Layer I low sample rate MPEG-2 Layer II low sample rate
Address : Type : Software Reset : Hardware Reset:
0x46-0x47-0x48-0x49-0x4A RO UND UND
Description The 34 bit PTS register contains the PTS value. When this value is read the corresponding interrupt bit is cleared (INT.PTS is cleared). USER - USER Data
7 0
4B Address : Type : Software Reset : Hardware Reset: Description When this register is read, the user interrupt is cleared (INT.USR is cleared). ERROR - ERROR Code
7 0
HEADLEN - Frame Length
7 44 45 HEADLEN[15:8] HEADLEN[7:0] 0
0x4B RO UND UND
Address : Type : Software Reset : Hardware Reset:
0x44-0x45 RO UND UND
Description The HEADLEN register contains the bit length of the compressed data frame HEAD[15:0]. The HEADER registers are all updated as soon as the decoder begins to decode a frame.
0F Address : Type : Software Reset : Hardware Reset: Description This register is a status register, when the host reads this register, this register and the corresponding interrupt register are cleared. The value in the ERROR register indicates the type of error that has occurred, seeTable 1. 0x0F RO 0 0
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STI4600
REGISTER DESCRIPTION(Cont'd) Table 3. Error register list
Error Name AC3 Decoding NO_ERROR EXPAND_DELTA_PAST_END_ARRAY XDCALL_TRY_TO_REUSE_REMAT_FLG XDCALL_TRY_TO_REUSE_COUPLING_STR A XDCALL_CANT_COUPLE_IN_DUAL_MODE XDCALL_TRY_TO_REUSE_CPL_LEAK XDCALL_TRY_TO_REUSE_SNR XDCALL_TRY_TO_REUSE_BIT_ALLOC XDCALL_TRY_TO_REUSE_COUPLING_EXP ONENT_STRA XDCALL_TRY_TO_REUSE_EXPONENT_STR A XDCALL_TRY_TO_REUSE_LFE_EXPONENT _STRA XDCALL_CHBWCOD_IS_TOO_HIGH BSI_ERR_REV BSI_ERR_CHANS CRC_NOT_VALID Packet synchronization SYNCHRO_PACKET_NOT_FOUND BAD_MPEGI_RESERVED_WORD BAD_MPEG2_RESERVED_WORD DIFF_first_access_pointer_AP_LENGTH UNKNOWN_STREAM_ID MARKER_ERROR UNKNOWN_SUB_STREAM_ID Value 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 17 18 19 20 21 22
.
Error Name Audio Synchronization UNKNOWN_SUB_STREAM_ID BAD_CRC_AC3 BAD_quantization_wordlength BAD_audio_sampling_freq BAD_MPEG_LAYER MPEG_BITRATE_FREE_FORMAT NOT_SUPPORTED_FRMSIZECOD BAD_CRC_MPEG_FRONT_END BAD_BIT_AFTER_LENGTH_FIELD_IN_MPEG _EXTENDED MPEG_EXTENDED_SYNC_NOT_FOUND MPEG decoding MPEG_EXTENSION_ERROR MPEG_MC_MUTE NOT USED (OLD MPEG_FS_CHANGE) NOT USED (OLD MPEG_EMPHASIS_CHANGE MPEG_LAYER_ERROR MPEG_CHCONFIG_ERROR MPEG_MC_PREDICTION_ERROR MPEG_CRC_ERROR MPEG_EXT_CRC_ERROR MPEG_TO_SMALL_FOR_MC_HEADER MPEG_BITRATE_ERROR Value 32 33 34 35 36 37 38 39 40 41 48 49 50 51 52 53 54 55 56 57 58
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REGISTER DESCRIPTION(Cont'd) 5.4.10 Decoding Registers STREAMSEL - STREAM Selection
7 0
PACKET_LOCK - Packet Lock
7 0
4F Address : Type : Software Reset : Hardware Reset: Description Number of packet use for synchronisation, max=1 min=0. AUDIO_ID_EN - Enable audio ID
7 0
4C Address : Type : Software Reset : Hardware Reset: Description
Value 0 1 2 3 Mode PES PES DVD Packet MPEG1 Elementary Stream
0x4C R/W NC UND
0x4F R/W NC UND
50 Address : Type : Software Reset : Hardware Reset: Description If set the decoders decode only the matching ID. AUDIO_ID - Audio ID
7 0
DECODESEL - Decoding Algorithm
7 0
4D Address : Type : Software Reset : Hardware Reset: Description
bit(2:0) 0 1 2 3 4 Mode AC3 Decoding MPEGI/II MPEGI/II extended PCM PINK NOISE generator
0x50 R/W NC UND
0x4D R/W NC UND
51 Address : Type : Software Reset : Hardware Reset: Description Matching ID for the Packet.
0
0x51 R/W NC UND
SYNCSTATUS - Synchronization Status
7
40 Address : Type : Software Reset : Hardware Reset: Description Status of the synchronization process. 0x40 R/W NC UND
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REGISTER DESCRIPTION(Cont'd) AUDIO_ID_EXT - Audio Extension
7 0
5.4.11 Post Decoding and Prologic DWSMODE - Downsampling Filter
7 0
52 70 Address : Type : Software Reset : Hardware Reset: 0x52 R/W NC UND
Description Matching ID for the Packet extension part. SYNC_LOCK - SYNC Lock
7 0
Address : Type : Software Reset : Hardware Reset: Description
0x70 R/W NC UND
This is an 8 bit register whose value controls the downsampling filter.
Value 0 1 2 Meaning Automatic (according to bitstream) Force Downsampling Suppress Downsampling
53 Address : Type : Software Reset : Hardware Reset: 0x53 R/W NC UND
PDEC - Post Decoder Register
7 6
Description Number of Audio frame use for synchronisation, max=3 min=0. Table 4. Sync Status bit mapping
Bit number selected mode 0 research syn word 1:0 Frame Status 1 Wait for confirmation 2 Synchronized 3 Not used 0 research syn word 3:2 Packet Status 1 Wait for confirmation 2 Synchronized 3 Not used
62 Address : Type : Software Reset : Hardware Reset: Description
5 4 DEM DCF
3
2
1
0 PL
0x62 R/W NC UND
This register is used to control the post decoder operations. DEM : When high the deemphasis filter is activated. DCF : When high the DC filter is activated PL : When high Prologic decoding is forced, when low the PL decoder is activated only if the output of the previous decoding stage is Pro Logic encoded.
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REGISTER DESCRIPTION(Cont'd) PL_AB - Prologic auto balance
7 0
5.4.12 Bass Redirection OCFG - Output Configuration
7 0
64 66 Address : Type : Software Reset : Hardware Reset: Description Setting this 8-bit register enables the auto balance function. The default value is zero (auto balance off). PL_DWNX - Prologic Downmix
7 0
0x64 R/W NC UND
Address : Type : Software Reset : Hardware Reset: Description
0x66 R/W NC UND
This register is 8 bit and should be loaded with a decimal number with value between 0 and 6. The values 5 and 6 are reserved for future variants. LP means Low pass filter. HP means High pass filter
Value Meaning The subwoofer is equal to the sum of all input channels. SUB=L+R+Ls+Rs+C+LFE Low frequencies are extracted from the input channels and redirected to the subwoofer. SUB=LP(L+R+Ls+Rs+C+LFE) Low frequencies are extracted from C, LFE, Ls and Rs channels and redirected to left and right channels. L=L+LP(C,LFE,Ls,Rs) R=R+LP(C,LFE,Ls,Rs) Low frequencies are extracted from the input channels and redirected to the subwoofer. 1 LSW SUB=LP(L,R,Ls,Rs,C,LFE) Low frequencies are removed from all channels. L=HP(L) R=HP(R) C=HP(C) 0 ALL Ls=HP(Ls) Rs=HP(Rs) All channels are rounded and scaled
65 Address : Type : Software Reset : Hardware Reset: Description This value in this register controls the function of the Prologic Downmix, seeTable 3. 0x65 R/W NC UND
4
SUM
3
SLP
2
LLR
Table 5. Prologic Downmix
Value 0, 1, 2 3 4 5 6 7 Comment Prologic is disabled 3/0 (L,C,R) three stereo 2/1 (L,R,S) phantom 3/1 (L,C,R,S) 2/2 (L,R,Sl, Sr) phantom 3/2 (L,C,R,Sl, Sl)
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REGISTER DESCRIPTION(Cont'd) PCMSCALE - PCM Scale Factor
7 0
BAL_SUR - L/R Surround Balance
7 0
67 Address : Type : Software Reset : Hardware Reset: Description This register is an 8 bit and loaded with the value of PCM scale. PCM scale is a master scale factor. It is expressed in 2 dB attenuation. Attenuation =-2k dB (where k is the register content). When k=0 the attenuation is not exactly 0 dB but it corresponds to a scale of 255/256. BAL_LR - Left/Right Balance
7 0
63 0x67 R/W NC UND Address : Type : Software Reset : Hardware Reset: Description This register is an 8 bit signed byte register (-128, +127) and controls the Left/Right surround balance. When the value is positive the Left channel is attenuated, when the value is negative the right channel is attenuated. The attenuation is done in steps of 0.5 dB. 5.4.13 AC3 Decoding DECODE_LFE - Decode LFE
7 0
0x63 R/W NC UND
4E Address : Type : Software Reset : Hardware Reset: Description This register is an 8 bit signed byte register (-128, +127) and controls the Left/Right channel balance. When the value is positive the Left channel is attenuated, when the value is negative the right channel is attenuated. The attenuation is done in steps of 0.5 dB. 0x4E R/W NC UND
68 Address : Type : Software Reset : Hardware Reset: Description When high decode LFE channel (if present) 0x68 R/W NC UND
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REGISTER DESCRIPTION(Cont'd) COMP_MOD - Compression Mode
7 0
RPC - Repeat Count
7 0
69 Address : Type : Software Reset : Hardware Reset: Description The value of this register defines the compression mode
Value 0 1 2 3 Meaning Line Out RF mode Custom 1 Custom 2
6C 0x69 R/W NC UND Address : Type : Software Reset : Hardware Reset: Description Repeat Count KARAMODE - Karaoke Downmix
7 0
0x6C R/W NC UND
6D Address : Type : Software Reset : Hardware Reset: Description Karaoke Downmix
Value Comment 0 Aware 1 Multichannel reproduction Downmix AC3 karaoke, Do not reproduce 2 V1/V2 3 Downmix AC3 karaoke, Reproduce V1 4 Downmix AC3 karaoke, Reproduce V2 5 Downmix AC3 karaoke, Reproduce V1 & V2
HDR - High Dynamic Range
7 0
0x6D R/W NC UND
6A Address : Type : Software Reset : Hardware Reset: Description 0x7F (0,99) 0x00 => no level LDR - Low Dynamic Range
7 0
0x6A R/W NC UND
Capable
6B Address : Type : Software Reset : Hardware Reset: Description 0x7F (0,99) 0x00 => no level 0x6B R/W NC UND
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REGISTER DESCRIPTION(Cont'd) DUALMODE - Dual Downmix
7 0
AC3_STATUS0 - AC-3 Status Register
7 0
6E Address : Type : Software Reset : Hardware Reset: Description Dual (1+1) Downmixr
Value 0 1 2 3 Comment Output as Stereo Output channel 1 on both output L/R Output channel 2 on both output L/R Mix channel 1 and 2 to monophonic and output on both L/R
76 0x6E R/W NC UND Address : Type : Software Reset : Hardware Reset:
Bit number 7 6:5 4:0
0x76 RO NC UND
Name Not-Used fs_cod Bitrate code
AC3_STATUS1 - AC-3 Status Register 1
7 0
77 Address : Type : Software Reset : Hardware Reset:
Bit number 7:4 3 2:0 Not-Used Lfe Acmod
DOWNMIX - Downmix
7 0
6F Address : Type : Software Reset : Hardware Reset: Description Downmix register, see table.
Value 0 1 2 3 4 5 6 7 8 Comment 2/0 Dolby Surround 1/0 Centre 2/0 (L,R) 3/0 (L,C,R) 2/1 (L,R,S) 3/1 (L,C,R,S) 2/2 (L,R,LS,RS) 3/2 (L,C,R,Ls,Rs) TBD
0x77 RO NC UND
Name
0x6F R/W NC UND
AC3_STATUS2 - AC-3 Status Register 2
7 0
78 Address : Type : Software Reset : Hardware Reset:
Bit number 7:5 4:0
0x78 RO NC UND
Comment
Name Bsmod Bsid
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STI4600
REGISTER DESCRIPTION(Cont'd) AC3_STATUS3 - AC-3 Status Register 3
7 0
AC3_STATUS5 - AC-3 Status Register 5
7 0
79 Address : Type : Software Reset : Hardware Reset:
Bit number 7:4 3:2 1:0
7B 0x79 RO NC UND
Comment
Address : Type : Software Reset : Hardware Reset:
Bit number 7:0
0x7B RO NC UND
Name Langcod
Name Not used Cmixlevel SurMixlevel
AC3_STATUS6 - AC-3 Status Register 6
7 0
AC3_STATUS4 - AC-3 Status Register 4
7 0
7C Address : Type : Software Reset : Hardware Reset:
Bit number 4:0
7A Address : Type : Software Reset : Hardware Reset:
Bit number 7:5 4:3 2 1 0
0x7A RO NC UND
Name Not used Dsurmod Copyright Origbs Lancode
0x7C RO NC UND
Name DialNorm
AC3_STATUS7 - AC-3 Status Register 7
7 0
7D Address : Type : Software Reset : Hardware Reset:
Bit number 7:6 5:1 0
0x7D RO NC UND
Name Room type Mix level Audprodie
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REGISTER DESCRIPTION(Cont'd) 5.4.14 MPEG decoding SKIP_LFE - SKIP LFE Channel
7 0
DRC - Dynamic Range Control
7 0
6A Address : Type : Software Reset : Hardware Reset: Description Dynamic range control (Future extension) MC_OFF - Multichannel 0x6A R/W NC UND
68 Address : Type : Software Reset : Hardware Reset: Description Skip LFE channel when On Decode Lfe channel when Off PROG_NUMBER - PROGRAM NUMBER
7 0
0x68 R/W NC UND
7
0
6D Address : Type : Software Reset : Hardware Reset: Description When set the multi channel part of the bitstream is not decoded, Only the MPEG1 compatible bitstream is decoded. 0x6D R/W NC UND
69 Address : Type : Software Reset : Hardware Reset: Description Select the Program #0 or #1 0: L0,R0 in front channels 1: L2,R2 in front channels MPEG_DUAL - MPEG Setup DUAL MODE
7 0
0x69 R/W NC UND
6E Address : Type : Software Reset : Hardware Reset: Description When Dual mode bitstream: 0 play only channel#1 1 play only channel #2 0x6E R/W NC UND
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STI4600
REGISTER DESCRIPTION(Cont'd) DOWNMIX - MPEG Setup
7 0
MP_STATUS1 - MPEG Status Register 1 77
7 6 SFR[1:0] 5 4 PAD PRI 3 2 MOD[1:0] 1 0 MEX[1:0]
6F Address : Type : Software Reset : Hardware Reset: Description See Table below. Karaoke Aware mode is defined for the DVD system by applying "second stereo" mode if MPEGII. MPEG Downmix
Value 0 1 2 3 4 5 6 Comment 1/0 2/0 3/0 2/1 3/1 2/2 3/2 (L,R) (L,C,R) (L,R,S) (L,C,R,S) (L,R,LS,RS) (L,C,R,Ls,Rs)
0x6F R/W NC UND
Address : Type : Software Reset : Hardware Reset: Description SFR[1:0] PAD PRI MOD[1:0] MEX[1:0] : : : : :
0x77 RO NC UND
Sampling Frequency Padding Bit Private Bit Mode Mode Extension
MP_STATUS2 - MPEG Status Register 2
7 6 X 5 X 4 X 3 C 2 1 0
78
X
OCB EMP[1:0]
MP_STATUS0 - MPEG Status Register 0 76
7 ID 6 5 LAY[1:0] 4 P 3 2 1 BRI[3:0] 0
Address : Type : Software Reset : Hardware Reset: Description Bits[7:4] C OCB EMP[1:0] : : : :
0x78 RO NC UND
Address : Type : Software Reset : Hardware Reset: Description ID LAY[1:0] P BRI[3:0] : : : :
0x76 RO NC UND
Not used Copyright Original/Copy Bit Emphasis rate index
Identifier Layer Protection Bit Bit rate index
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STI4600
REGISTER DESCRIPTION(Cont'd) MP_STATUS3 - MPEG Status Register 3 79
7 6 CEN[1:0] 5 4 SUR[1:0] 3 2 1 0 LFE AMX DEM[1:0]
MP_STATUS5 - MPEG Status Register 5
7 6 5 4 3 2 1 0
7B Address : Type : Software Reset : Hardware Reset: Description 0x7B RO NC UND
Address : Type : Software Reset : Hardware Reset: Description CEN[1:0] SUR[1:0] LFE AMX DEM[1:0] : : : : :
0x79 RO NC UND
Centre Surround LFE Audio mix Dematrix procedure
The number of extended ancillary data bytes is contained in this register
MP_STATUS4 - MPEG Status Register 4
7 6 5 NML[2:0] 4 3 2 1 0 CIS
7A EXT
MFS MLY CIB
Address : Type : Software Reset : Hardware Reset: Description EXT NML[2:0] MFS MLY CIB CIS : : : : : :
0x7A RO NC UND
Extension bitstream present Number of Multi-lingual Channels Multi-lingual FS Multi-lingual Layer Copyright ID Bit Copyright ID Start
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STI4600
6 GENERAL INFORMATION
6.1 PACKAGE MECHANICAL DATA Figure 14. 80-Pin Plastic Quad Flat Package
Dim A A2 D D3 E E1 E3 e ND NE N
mm Min Typ Max 3.40 Min
inches Typ Max 0.134
2.55 2.80 3.05 0.100 0.110 0.120 22.95 23.20 23.45 0.904 0.913 0.923 18.40 0.724
D1 19.90 20.00 20.10 0.783 0.787 0.791 16.95 17.20 17.45 0.667 0.677 0.687 13.90 14.00 14.10 0.547 0.551 0.555 12.00 0.80 24 16 80 0.472 0.031
Number of Pins
Information furnished is believed to be accurate and reliable. However, SGS-THOMS ON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result fr om its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of SGS-THOMSON Microelectronics. (c)1997 SGS-THO MSON Microelectronics - All rights reserved. Purchase of I2 C Components by SGS-THOMSON Microelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an I2C system is granted provided that the system conforms to the I 2C Standard Specification as defined by Philips. Dolby(R), Dolby Pro Logic(R) and Dolby AC-3(R) are registered trademarks of DOLBY LABS. SGS-THOMSON Microelectronics Group of Companies Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A .
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